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https://teapaw.org/t.co/x7VAAFm1Ep

Palo Alto, California
Joined August 2025
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We gave our AI system a spec, and in under 2 weeks, it designed, verified, and deployed a chip that beats NVIDIA. It’s built for low-power physical AI workloads. We’re running live inference on >B+ parameter models like Llama, Qwen, and Kimi, serving at 3.4x better perf/watt than NVIDIA Jetson. From just a specification, our AI system autonomously generated all of the RTL Design, UVM verification, formal proofs, firmware, drivers, and kernels, co-designing the model, software and silicon as one optimization loop. Better AI can now design better chips to run AI, leading to a loop of recursive-self improvement towards our path to abundant intelligence.
Readers added context they thought people might want to know
Architect Labs did not manufacture a physical chip; the design was tested on a commercial AMD Versal FPGA board. Furthermore, the 3.4x perf/watt gain over NVIDIA Jetson is a simulation-based projection for a future 8nm ASIC, not a physical benchmark. businessinsider.com/architect-labs… architectlabs.com/architect-labs…
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Architect Labs is excited to be a part of this! AI & mathematics will have a large impact on all engineering disciplines, including chip design. We're looking forward to seeing what open problems get solved 👀
We partnered with @AnthropicAI @OpenAI to host the world's first math hackathon. 40 hours, $2M compute - solve, understand, and present an open problem. Applications are live: mathathonchallenge.com
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2 weeks from initial idea to fully verified, deployed, and end-to-end working RTL. All the code for the ASIC is done, and we've shown a sample of it running on FPGA. We're working hard to bring it to GDS and take it to TSMC. Read more below:
We gave our AI system a spec, and in under 2 weeks, it designed, verified, and deployed a chip that beats NVIDIA. It’s built for low-power physical AI workloads. We’re running live inference on >B+ parameter models like Llama, Qwen, and Kimi, serving at 3.4x better perf/watt than NVIDIA Jetson. From just a specification, our AI system autonomously generated all of the RTL Design, UVM verification, formal proofs, firmware, drivers, and kernels, co-designing the model, software and silicon as one optimization loop. Better AI can now design better chips to run AI, leading to a loop of recursive-self improvement towards our path to abundant intelligence.
Readers added context they thought people might want to know
Architect Labs did not manufacture a physical chip; the design was tested on a commercial AMD Versal FPGA board. Furthermore, the 3.4x perf/watt gain over NVIDIA Jetson is a simulation-based projection for a future 8nm ASIC, not a physical benchmark. businessinsider.com/architect-labs… architectlabs.com/architect-labs…
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Our co-founder and CEO Ebrahim Hussain (@axi_master) sat down with Schuster Tanger from @TQVentures to discuss the next shift in computing paradigms. The conversation covers why intelligence is scaling and fragmenting at the same time, across gigawatt data centers, robotics, autonomous systems, defense, wearables and personal AI, and why each of those needs chip designs that are co-designed and co-evolved for its own workload. Ebrahim also talks through what he learned building silicon at Apple and Tesla, why more companies will vertically integrate to co-design their own silicon, and how Architect Labs is building the technology that makes world-class chip design available to anyone with a workload that matters. Full conversation in the thread below
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Today, getting from concept of silicon runs multiple years. Hundreds of millions of dollars in upfront investment. A design flow that has only incrementally changed in the last four decades. Our co-founder & CEO, @axi_master sat down with Schuster Tanger from @tqventures to discuss the future of custom silicon, closing the loop between AI and chip design, and how Architect Labs is building a fundamentally new approach to going from software to silicon in a fraction of today’s timelines. Full video releasing soon…
The future of custom chip design. The next Study. Coming soon.
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The world needs far more chip designs than the industry can produce today. AI workloads change every few months, and they are spreading beyond data centers into robotics, defense, wearables, and nearly every device around us. The silicon underneath still takes years and hundreds of millions of dollars to build, and the expertise to do it sits with a few hundred people at a handful of companies. That gap is why @architectlabs exists. In a new @DanielNenni (semiwiki) feature, our co-founders @axi_master and @aadityasubedi_ share the company's vision to reimagine how the world gets from software to silicon. We are building an end-to-end AI system that designs and verifies chips, so any organization or sovereign nation with a demanding workload can co-design the hardware towards the industry's path to superintelligence. Read the full piece in the thread:
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IEEE International Conference on LLM-Aided Design #ICLAD2026 kicks off today at @Stanford, and @architectlabs is proud to be a sponsor. It's great to see the research community pushing the boundaries of AI for chip design. Earlier today, Armin Abdollahi from our research team, took the stage to present his PhD research work on pre-synthesis timing prediction from Verilog. Getting timing feedback before synthesis is one of the long-standing bottlenecks in the design loop, and it's exciting to see his research tackling it head on. At @architectlabs, we're building a new way to design an verify chips with AI, and conferences like ICLAD are exactly where these ideas take shape. We're also at the career fair today, so come find us at our table. #AI #ChipDesign #Semiconductors
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if you're interested in the intersection of AI, silicon, and systems, consider joining us - jobs.ashbyhq.com/architect
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The industry narrative says AI is transforming chip design. The data says otherwise. The industry has been adopting RTL copilots, DV agents, PD optimizers, and companies claim 3x, 10x, even 400x speedups on individual tasks. Yet first-silicon success rates have fallen to a 20-year low, and spec-to-silicon timelines have barely moved. Task-level wins are not translating into program-level outcomes. Yesterday at #DAC2026, our CEO @axi_master and Head of IP, @ekinthesumbul shared why, and what we're doing about it. Rather than bolting AI to current design flows, we at @architectlabs have built a new way of designing and verifying chips in the age of AI. It is a unified stack spanning models, specialized agents, accelerated-EDA tools, and new design methodologies, all built to empower the Human Architect to drive a design end-to-end, from software to silicon in a fraction of today's timelines. We believe more and more companies will design their own custom chips, co-designed with their workloads and our AI system will not just write RTL. It will co-design the whole stack from software to silicon: firmware, kernels, RTL, and eventually the AI models and workloads themselves. Today, Final Day of DAC 2026, Stop by our booth to see a live demo of our AI system autnonomously designed, verified, and deployed an AI acclerator it can run on. #DAC2026 #AI #ChipDesign #Semiconductors
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Day 2 at DAC, come see our demo at booth 943! If you haven't stopped by yet to see our demo, we have an AI chip that our system designed, verified, and deployed in under two weeks with zero human involvement. We're running it live all day and will be presenting more about it at 3:15 today in the Exhibitor Forum!
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We're proud to sponsor ICLAD 2026. Join us July 30–31 at Stanford University for two days to learn about what is happening at the intersection of AI and chip design. Our AI and hardware researchers will be there both days, ready to talk about what we've been building. Find us Thursday at the Career Fair, if you're thinking about your next move in silicon and AI. Check out the full program and plan your visit: iclad.ai/program See you at Stanford. #ChipDesign #AI
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We are thrilled to announce that Dan Ganousis has joined @architectlabs as Head of Sales. Dan has spent decades at the forefront of the semiconductor industry. He witnessed and led the adoption of RTL firsthand and helped drive the wave of transformation led by the major EDA companies, the shift that redefined how the world designs chips today. Over decades, he has led sales and marketing organizations at Tenstorrent, SiFive, Hewlett-Packard, and Mentor Graphics, and has founded two silicon startups, one of which was acquired by Xilinx. Now, a new transformation in chip design is underway, and Dan will be spearheading it at Architect Labs, leading our sales organization, our strategic accounts, and key industry partnerships. Few people have seen this industry evolve the way Dan has. Fewer still have shaped it. We could not be more excited to have him on board as we build what comes next.
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We're heading to DAC 2026. Find us at Booth 943, July 27-29 at the Long Beach Convention Center. We'll be showing what we've been building, with live demos and real hardware up and running. Our AI and hardware researchers will be around all three days, and we're giving a presentation during the show as well. There's swag and gifts waiting for everyone who stops by. If you're working anywhere in the chips-to-systems world, come meet us. Bring your hardest questions, our researchers like those best. Come say hi, or grab time with us ahead of the show for 1-1 or deeper discussions: architectlabs.com/blog/dac20… See you in Long Beach. #DAC2026 #ChipDesign #AI
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We at @architectlabs are hiring across the board. We’re looking for exceptional people, across Palo Alto and Bangalore, excited to work at the intersection of frontier AI, systems, and silicon. If that sounds exciting, consider joining us: architectlabs.com/careers
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Our launch last week, spotted in Times Square. Thanks to everyone, and we are just getting started!
Today, @aadityasubedi_ and I are excited to introduce @architectlabs. We are building the AI system to design and provably verify chips for the world's most demanding workloads. AI scaling is fundamentally changing the economics of hardware infrastructure. As models scale, become more capable, and more widely deployed, the bottleneck is shifting from software and models alone to the physical infrastructure that runs it: specialized compute, memory, networking, interconnects, and full-stack system design. General-purpose hardware is no longer enough, and the world is racing to spin up new chip programs. This is not just true across datacenter training and inference, but everywhere AI enters the physical world: robotics, autonomous systems, spatial computing, defense, personal devices, industrial automation, and scientific instruments. But designing a chip today remains one of the most gated efforts in modern technology. A modern chip program takes years, costs hundreds of millions of dollars, and depends on a shrinking pool of expertise concentrated inside a small number of companies. Architect Labs is a foundational lab building an AI system that designs and provably verifies chips end-to-end. We partner with semiconductor and workload companies, AI labs, and nations to turn demanding workloads into purpose-built chips, on demand at scale. We aim to drastically accelerate chip design, so that the models, software and chip designs can co-evolve together, accelerating the industry’s path to superintelligence. Two decades ago, the fabless revolution made it possible to build a chip company without owning a fab. TSMC made world-class manufacturing available to anyone with a design. We aim to do the same for chip design itself: enable any organization with a workload, or specification, to get a purpose-built chip design that unlocks scale and distribution of intelligence impossible with current hardware paradigms. Our founding team collectively has taped out 80+ production chips, led $10B datacenter product lines, been core contributors to Meta’s AI silicon, architected and designed one of the first neuromorphic chips out of Intel, led research teams at Anthropic, xAI, and Google DeepMind, and contributed to fundamental AI research across nearly every frontier lab. We have already partnered with semiconductor companies to accelerate their chip programs, and some of our AI-generated chip designs are going to tape out on leading-edge foundry nodes later this year. We’ve also raised a $24M seed round led by @stevejang from @KindredVentures , with participation from @TQVentures , @RaceCapital , @scaletogether , @ora, and Link Ventures. We are grateful for the support of our angels and advisors, including @snsf , @lukaszkaiser , @AravSrinivas , Kunle Olukotun, @tlbtlbtlb, @alexwg, Siddharth Nath, Thierry Tambe, @arashf , @ekaurghar, @CHHubbell, Selene Casabal, @semiDL , and engineering leaders from OpenAI, NVIDIA, Google DeepMind, Intel and more. The next great scaling law may not come from the models alone. It will come from making the physical substrate of intelligence programmable. We exist to bring this future to life.
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Grateful to have @stevejang from @KindredVentures lead our seed. We are excited to build alongside investors who understand the full computing stack, believe deeply in the mission, and are able to look at long time horizons on where the industry is headed.
Architect Labs is developing AI to accelerate the co-design of custom chips - democratizing the capabilities to innovate on the hardware level of the incredible intelligence era ahead of us. So, we’re thrilled today to share that @KindredVentures led a $24M seed round for @architectlabs, joined by @TQVentures @RaceCapital @togetherfund, as well as a storied group of operators/researchers including @snsf, @lukaszkaiser, @AravSrinivas, @tlbtlbtlb, @alexwg, and et al from @NVIDIA, @GoogleDeepMind, @OpenAI, and @perplexity_ai. For decades, the contract between hardware and progress was simple: transistors got smaller, everything got faster, and the industry planned around the rhythm. That rhythm has slowed because of Moore’s Law stalling, and the new performance gains are coming from somewhere else entirely, architectural decisions about how memory and compute are arranged, how silicon is shaped around the workloads it serves, and how hardware and software are designed to evolve together instead of drifting apart. AI is no longer confined to the data center. It’s running in robots, at the edge, on satellites, in every device with ambition. Each of those environments has its own physics around power, latency, and cost, and none of them are well-served by the same general-purpose GPU. The frontier labs building tomorrow's models are still optimizing upward to fit chips they didn't design, instead of designing chips downward to fit the models they imagine. The reason that hasn't changed is not just physics, it’s also inertia. Chip design cycles remain long, manual, capital-intensive, and gated by a small population of specialists. Custom silicon has remained an inheritance of a few incumbents rather than a tool available to the new guard who need it. Architect Labs is rebuilding that process from first principles, an AI-native, self-improving system that co-designs silicon, compilers, runtimes, and system software as a single loop, so the cadence of chip development can finally start to look like the cadence of software. It's the unlock that lets the companies shaping intelligence actually own the hardware that runs it. The founders, @axi_master and @aadityasubedi_ understand exactly how to diagnose this problem. They have little patience for the status quo. Ebrahim started college at 15, found his way onto Apple's silicon teams, and then onto Tesla's AI5 (the custom chip behind FSD and Optimus) where he watched a piece of silicon become outdated by the models it was meant to serve before it even shipped. Aaditya was researching AI for code verification at Harvard before he and Ebrahim met at Stanford and started working on AI for chip design together, a collaboration that later became the company. Alongside them now is a stellar team, researchers and systems engineers from @Anthropic, @Google, @intel, @Meta, @Samsung and @xai, with 80+ production tape-outs and core contributions at nearly every frontier lab between them. To the Architect Labs team, we’re honored to join you on this incredible mission! 🚀🚀🚀
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We are proud to announce @architectlabs. Our mission is to build an AI system that designs and provably verifies chips end-to-end. By doing so, we unlock a new era of purpose-built chips generated on demand, that powers the scale and distribution of intelligence impossible with current hardware paradigms. Our founding team collectively has taped out 80+ production chips, led $10B datacenter product lines, been core contributors to Meta’s AI silicon, architected and designed the first neuromorphic chip out of Intel AI Lab, led research teams at Anthropic, xAI, and Google DeepMind, and contributed to fundamental AI research across nearly every frontier lab. We’re fortunate to be backed by investors who share our vision, including @stevejang from @KindredVentures who led our $24M seed round as well as @TQVentures , @RaceCapital , @scaletogether , @ora , and Link Ventures. We are also grateful for the support of our angels and advisors, including @snsf, @lukaszkaiser, @AravSrinivas, Kunle Olukotun, @tlbtlbtlb, @alexwg, Siddharth Nath, Thierry Tambe, @arashf, @ekaurghar, @CHHubbell, Selene Casabal, @semiDL and engineering leaders from OpenAI, NVIDIA, Google DeepMind, Intel and more. We’ve come together to scale up and reinvent how chips are designed and provably verified end-to-end. If you want to work at the intersection of frontier AI, systems and silicon, consider joining us.
Today, @aadityasubedi_ and I are excited to introduce @architectlabs. We are building the AI system to design and provably verify chips for the world's most demanding workloads. AI scaling is fundamentally changing the economics of hardware infrastructure. As models scale, become more capable, and more widely deployed, the bottleneck is shifting from software and models alone to the physical infrastructure that runs it: specialized compute, memory, networking, interconnects, and full-stack system design. General-purpose hardware is no longer enough, and the world is racing to spin up new chip programs. This is not just true across datacenter training and inference, but everywhere AI enters the physical world: robotics, autonomous systems, spatial computing, defense, personal devices, industrial automation, and scientific instruments. But designing a chip today remains one of the most gated efforts in modern technology. A modern chip program takes years, costs hundreds of millions of dollars, and depends on a shrinking pool of expertise concentrated inside a small number of companies. Architect Labs is a foundational lab building an AI system that designs and provably verifies chips end-to-end. We partner with semiconductor and workload companies, AI labs, and nations to turn demanding workloads into purpose-built chips, on demand at scale. We aim to drastically accelerate chip design, so that the models, software and chip designs can co-evolve together, accelerating the industry’s path to superintelligence. Two decades ago, the fabless revolution made it possible to build a chip company without owning a fab. TSMC made world-class manufacturing available to anyone with a design. We aim to do the same for chip design itself: enable any organization with a workload, or specification, to get a purpose-built chip design that unlocks scale and distribution of intelligence impossible with current hardware paradigms. Our founding team collectively has taped out 80+ production chips, led $10B datacenter product lines, been core contributors to Meta’s AI silicon, architected and designed one of the first neuromorphic chips out of Intel, led research teams at Anthropic, xAI, and Google DeepMind, and contributed to fundamental AI research across nearly every frontier lab. We have already partnered with semiconductor companies to accelerate their chip programs, and some of our AI-generated chip designs are going to tape out on leading-edge foundry nodes later this year. We’ve also raised a $24M seed round led by @stevejang from @KindredVentures , with participation from @TQVentures , @RaceCapital , @scaletogether , @ora, and Link Ventures. We are grateful for the support of our angels and advisors, including @snsf , @lukaszkaiser , @AravSrinivas , Kunle Olukotun, @tlbtlbtlb, @alexwg, Siddharth Nath, Thierry Tambe, @arashf , @ekaurghar, @CHHubbell, Selene Casabal, @semiDL , and engineering leaders from OpenAI, NVIDIA, Google DeepMind, Intel and more. The next great scaling law may not come from the models alone. It will come from making the physical substrate of intelligence programmable. We exist to bring this future to life.
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Sneak peek into a project our research team has been working on. In an experiment, we post-trained an open-source model for RTL design, using RLVR. The primary objective was to ensure functional correctness by actually compiling and simulating the Verilog. The result, Architect v0.1, matches the closed-source frontier, Claude Opus 4.6 at the time of the experiment, and beats GPT-5.4 on the non-agentic CVDP (Comprehensive Verilog Design Problems) benchmark from NVIDIA Research. In this experiment, no agent harness or test-time scaling methods were used, and rather it was to show hillclimbing using curriculum learning and reward shaping with a limited dataset.
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