hardware accelerated cryptography
Joined October 2018
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Supranational retweeted
Wormhole Foundation has awarded a Contributor Grant to @_Supranational for Wormhole ZK hardware acceleration.
This step is crucial for minimizing trust and enhancing security of the multichain ecosystem powered by @Wormhole.
Supranational retweeted
1) Faster/Cheaper implementations of Groth16
Proofs are a large cost for Storage Providers in Filecoin, so we spent engineering time to make them faster.
See 2021 numbers:
xitter.cf/Filecoin/status/166102…
Only this year we have a 6x speedup thanks to @_Supranational!
zk-SNARKs (Zero-Knowledge Succinct Non-Interactive Argument of Knowledge) provide the ability for one party to prove to another that they know a secret without revealing the secret itself.
Filecoin is the largest deployed zk-SNARK network to date. 🤯research.protocol.ai/sites/s…
Supranational retweeted
We are excited to announce our partnership with Supranational, working on the next iteration of VDFs (you all lovingly know them as Timelords) to help make our PoST network better than ever!
businesswire.com/news/home/2…
Supranational retweeted
🔊This week, we cover hardware for ZKPs and VDFs! @AnnaRRose & @tarunchitra chat with Simon Peffers & @kellymolson from @_Supranational. They share their knowledge of FPGAs, ASICs and how it all ties into Moore’s law, ZK cryptography and blockchains!
zeroknowledge.fm/170
Introducing 'blst', a BLS12-381 signature library
medium.com/supranational/int…
Supranational retweeted
This is the first post in a series of progress blogs by Principal Researcher Joey Dodds (@n1nj4.) He introduces the ‘blst’ BLS verification project, a new collaboration between Galois, @_Supranational, @protocollabs, and @ethereum. Check it out: buff.ly/3c7oWjZ
Learn about different proof techniques for Verifiable Delay Functions: link.medium.com/fj2LtexoI8
Round 3 winner of the VDF FPGA competition, Benjamin Devlin, writes about low latency multipliers on the Jane Street Tech Blog: blog.janestreet.com/really-l…
New paper out by Sabanci University summarizing low-latency ASIC algorithms for use in VDFs: eprint.iacr.org/2020/480
In this post we'll synthesize the learnings from our ASIC design studies to arrive at an initial design and implementation of the OpenVDF modular squaring unit: medium.com/supranational/ope…
Learn about the impact of coefficient size for the polynomial multiplier used in the Open VDF project: medium.com/supranational/ope…
We explore low latency partial product generation in our most recent Open VDF blog: medium.com/supranational/ope…
Learn about low latency carry save adders in the Open VDF design: medium.com/supranational/ope…
Carry propagate adders in the Open VDF design: link.medium.com/oZQ8GRtlt5
An overview of the Ozturk multiplier used in the Open VDF design: link.medium.com/OP5AUnVno5
Introducing the Open VDF ASIC: link.medium.com/kwyNb9Kko5
Supranational retweeted
Transcript: "Hardware Accelerated RSA - VDFs, SNARKs, and Accumulators" diyhpl.us/wiki/transcripts/s… @_Supranational @CBRStanford #SBC20
Congratulations to Eric Pearson, the round 1 winner in the VDF FPGA competition. Eric increased the throughput of the baseline design by 78% and won $64,200. vdfalliance.org/news/fpga-co…
Two new prizes also announced, ending Jan 30.
#1 - $5,000 for fastest alternative algorithm implementation on FPGA
#2 - $5,000 for best research paper exploring low latency RSA VDF algorithms
Official rules here: supranational.atlassian.net/…
Want to learn more about our open source hardware project? Check the wiki for more information 👀supranational.atlassian.net/…