Compilers are an important part of our customizable and secure RISC-V processor offering. Ramkumar Ramachandra, one of our compiler experts, was presenting about his work at the recent EuroLLVM Developers' Meeting. See the recording of his talk below 👇
youtube.com/watch?v=2Gs-eAKu…
#ICYMI Developing memory-safe software with CHERI has never been easier!
Read our recent press release on Codasip Prime to learn more.
codasip.com/press-release/20…
Enabling early software development is very important. At Codasip we realize that and provide number of simulation models with our customizable RISC-V processors. Now including MachineWare's SIM-V.
codasip.com/2025/04/22/machi…
#RISCVSummitEurope highlight!
Using CMSIS for simplified migration to RISC-V
Wed 14 at 10:35, in Louis Armand East (S3)
By Keith Graham, Vice President of University and Customer Experience Program, Codasip.
#ICYMI We have launched Codasip Prime for #CHERI featuring a high-performance FPGA system, including the processor and peripherals, and a full software development kit.
Learn more: codasip.com/press-release/20…
We are excited for RISC-V Summit in Paris next week. If you are going, make sure to attend the automotive panel.
📅 Wednesday May 13 at 17:15
Learn more: codasip.com/events/risc-v-su…
Codasip Studio is now integrated with MachineWare’s SIM-V simulator. Learn more 👇
codasip.com/2025/04/22/machi…
🔔 Press release: Codasip launches complete exploration platform to accelerate CHERI adoption
codasip.com/press-release/20…
The winners of the RISC-V Hackathon online have been revealed! Check out the top solutions and learn more about the customization challenge we presented to the contestants.
youtu.be/6HtgXuuyP1s?si=yZmm…
We are excited to announce the latest release of Codasip Studio, packed with features to streamline and enhance the custom processor design journey. One of the feature highlights of this release is the integration with MachineWare’s SIM-V simulator.
codasip.com/2025/04/22/machi…









