@SynthWorks

VHDL Verification Specialist, OSVVM author, VHDL Trainer, Yogi

SynthWorks.com
Joined April 2009
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Online Advanced VHDL Verification Training Courses - September - mailchi.mp/firsteda.com/upco…
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Been working on an SPI to AXI4-Lite bridge recently. A beta version is now available on GitHub: github.com/airhdl/spi-to-axi… Thanks to @SynthWorks and @Sigasi for helping out.

GitHub - airhdl/spi-to-axi-bridge: An SPI to AXI4-lite bridge for easy interfacing of airhdl...

An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller. - airhdl/spi-to-axi-bridge

github.com
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Lately, me and @unaimarcor worked on github.com/pyTooling/Actions to simplify #githubactions for #Python projects. It supports: unit testing (#pytest), code coverage, static type checking (#mypy), packaging, publishing to PyPI, test reports and Sphinx documentation on GH pages.
Example workflow testing and packaging a Python project and publishing tagged versions to PyPI.

ALT Example workflow testing and packaging a Python project and publishing tagged versions to PyPI.

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This is pretty much what the rest of the world thinks about American🇺🇸 health care. We have no idea why you put up with, it just looks insane to the rest of us. You're all nuts! 🤷‍♂️
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Jim Lewis retweeted
Unai@unaimarcor1 Jun 2021
To all the VHDL people out there, do you now about IEEE-P1076.gitlab.io? That's the site of the VHDL Analysis and Standardisation Group (VASG). We are gathering and organising Bug Reports and Capability/Feature Request for the next revision of the language (202X). Come by!
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Tonight we will file a lawsuit in federal court against U.S. Department of Homeland Security, U.S. Marshals Service, U.S. Customs and Border Protection, and the Federal Protection Service alleging they seized and detained Oregonians without probable cause. Statement here:
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OSVVM's MemoryPkg is great for modelling large, sparse RAMs github.com/OSVVM/OSVVM/blob/…
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Jim Lewis retweeted
Srinivasan V@sricvc11 Sep 2015
And there comes intelligent coverage driven verification #dvcon #osvvm #vhdl @SynthWorks
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Jim Lewis retweeted
Srinivasan V@sricvc7 Sep 2015
Replying to @SynthWorks
@SynthWorks That would make it 3 days of #OSVVM across the globe - on Friday we've a paper on #OSVVM with Assertions @dvcon India!
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Got it! #OSVVM in #VHDL gets 100% fcov closure faster than #SystemVerilog #UVM - good doc on OSVVM UG @AldecInc and @SynthWorks
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Jim Lewis retweeted
Aldec, Inc.@AldecInc2 Mar 2015
[ON-DEMAND WEBINAR] #OSVVM Advanced Verification for VHDL w/ @SynthWorks dld.bz/duXA6
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Jim Lewis retweeted
Aldec, Inc.@AldecInc2 Jun 2014
LIVE! Jim Lewis from Synthworks presenting OSVVM at the Aldec booth 1521! #51DAC
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