Designing Physical AI Systems Under Real-World Constraints Where latency, power, reliability and data movement shape system behavior Physical AI extends artificial intelligence into systems that sense, interpret and... Read the Cadence Tech Talk article>> ow.ly/6Blj50ZXq8W

Renesas Expands GaN Portfolio with First Low-Voltage GaN FETs for AI Data Centers and Robotics New 100V E-mode GaN Advanced Power Transistor Family Delivers Higher Power Density and Industry-Leading Figure-of-Merit Performance ow.ly/2BxQ50ZYEtm

aiMotive and Cadence Demonstrate Layer-by-Layer Workload Placement Across Independent AI Engines ow.ly/ZCsz50ZStuX

Silicon-Proven Bluetooth® 6.3 RF IP Cores for Next-Generation Advanced Wireless SoCs - T2M ow.ly/ln8N50ZXqiX

Cadence Expands ChipStack AI Super Agent with a New Agent for RTL Generation and Early PPA Optimization New AI agent leverages core EDA technologies to both create RTL from specifications and upgrade RTL with signoff grade quality and performance... ow.ly/lMjA50ZQlpB

Renesas Introduces Smallest Configurable GreenPAK IC with Multi-Time Programmability in Ultra-Compact WLCSP and STQFN Packages ow.ly/vgCi50ZYEzj

From Gate-All-Around to Complementary FETs: What’s Next in Transistor Scaling Two years ago, we introduced why the industry was moving to gate‑all‑around (GAA) transistors and how foundation IP co-optimized with... Read the Synopsys Tech Talk article>> ow.ly/ryGB50ZOxyf

The Intersection Of AI And Voice At The Edge Increasingly capable natural language processing is changing how audio systems are designed, integrated, and perceived... Watch now>> ow.ly/5rbb50ZPUiR

New MIPI Alliance Kinematics Working Group to Standardize Streaming Format for Radar and Lidar Sensor Data ow.ly/swKA50ZQlBw

GUC Announces 2nm 16 Gbps HBM4E IP Its HBM4E PHY and Controller IP is design-ready and has been adopted in customer AI ASICs. Implemented on TSMC’s cutting-edge N2P process, the HBM4E PHY has successfully taped out on TSMC CoWoS®-L advanced packaging... ow.ly/XGFe50ZQgGH

Cadence HBM4/4E at 14Gbps Cadence HBM4/4E PHY IP sets the benchmark for high-speed memory interfaces. In this demo, our engineers showcase the performance and robustness of the PHY operating at 16 Gbps and 18 Gbps TX speed, while reading/writing to the... ow.ly/sEAv50ZQibp

Cadence Collaborates with TSMC to Deliver Certified Tool Solutions and Industry-Leading, Silicon-Proven UALink IP on TSMC Advanced Processes Expanded partnership spans TSMC A14 certification, silicon-proven IP on TSMC N3P/N2P, wafer-scale 3D-IC for... ow.ly/s9Ku50ZQKTK

T2M Advances RISC-V CPU IP Cores Portfolio for Next-Generation AI and Intelligent Edge SoCs ow.ly/nUMs50ZThAz

Renesas Unveils Industry's First 650V GaN in Dual-Side Cooled 8x8mm Package for Megawatt-Scale AI Data Centers ow.ly/eSq250ZYEkX

QuickLogic Secures Six-Figure eFPGA IP Contract for Automotive Industrial SoC Initial contract targets battery management and motor control applications using 16nm automotive process technology ow.ly/62CU50ZYhvM

Silicon Creations Receives 10th Consecutive TSMC OIP Partner of the Year Award for Mixed Signal IP Recognition reflects over 15 years of collaboration and production success supporting customers across advanced TSMC process technologies ow.ly/oaar50ZSnis

OpenAI and Synopsys Announce GPT-Synopsys: Frontier Intelligence to Revolutionize Chip Design ow.ly/Vz2W50ZThJN

Introducing eUSB2V2: Modernizing USB2.0 for Edge AI and AI PC Platforms Join the November 17th webinar as we introduce eUSB2V2 fundamentals and explore how Cadence’s IP solution helps bridge legacy USB and next-generation system requirements. Register Now ow.ly/9xXm50ZXm5a

2026 TSMC Global OIP Ecosystem Events Join Us to Connect, Collaborate, and Shape the Future of AI. Get ready to immerse yourself in the future of semiconductor design at the 2026 TSMC Global Open Innovation Platform® (OIP) Ecosystem Forum! Save the date ow.ly/sET750ZBFS2

intoPIX to Demonstrate JPEG XS, IPMX and SMPTE ST 2110 Solutions at NAB Show New York 2026 ow.ly/aYW150ZYhr7