@splinedrive

Life’s too short for someone else’s silicon.

Joined November 2012
  • Tweets24.3K
  • Following368
  • Followers21.4K
5.3KMedia
ASIC Design Silicon Proven @machdyne topaz
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I ♥️ski aggu
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Matthew Venn@matthewvenn12h
Photolithography is the #ASIC terminology of the week! zerotoasiccourse.com/termino… In the last month, Photolithography has been the 24th most popular out of 42 terms.

Photolithography

Photolithography is the repeating process of coating a wafer with light-sensitive resist, exposing it through a mask, and etching the pattern to build up the many layers that form an IC.

zerotoasiccourse.com
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psychogenic
@PsychogenicTechOct 24
New form-factor for GF180 TT ASICs panelized for wirebonding. Can be used as a raw IC or have designs loaded and/or clocked by the CH32 MCU, while giving external circuitry access to all I/O along with a USB TUI, using github.com/psychogenic/TT-DI… (built on the amazing ch32fun lib).
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Ayaan 🐧
@twtayaanOct 23
Linus Torvalds uses Claude for Linux, but doesn’t want your AI code if you don’t understand it. He wants “competent people to use AI as a tool” and criticizes drive by patches from people who don’t understand their submissions. Newcomers are welcome, as long as they’re willing to learn and understand the code they submit. Linus also identifies another problem. AI is finding real bugs, adding work for already overloaded maintainers. His position is clear. Use AI, but understand the code you submit. Full story: theregister.com/columnists/2…
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Chris@criccominiOct 23
Rust has kind of become unusable for me with AI and worktrees… Between the compile times and the disk usage, it’s a huge tax. I’m working in a C++ codebase right now and it’s such a breath of fresh air… I never thought I would say that
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Marcelo Samsoniuk
@samsoniukOct 24
wow! this is crazy! 🔥🔥🔥
Tak 🦞
@cherry_mx_redsOct 23
OpenAI's AI agents figured out how to secretly communicate between isolated virtual machines using CPU cache timing. No internet. No network connections. No shared files. Imagine two prisoners in solitary confinement discovering they can communicate by tapping on a shared wall. Except the wall was a CPU cache.
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logic destroyer
@splinedriveOct 23
xitter.cf/splinedrive/status/179…
logic destroyer
@splinedrive1 Jun 2024
I motivated my 9-year-old son to develop an 8-bit binary counter as an ASIC using Wokwi, following certain instructions. Here is the result. @WokwiMakes @tinytapeout @UriShaked @matthewvenn #wokwi #asic #dff #binary #counter #revolution #logicDestroyer generation change, game changer The future belongs to our KID chip designers.
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Father and son. No FPGA, no ASIC. Just jumps and downhill.
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My son Kian was only nine years old when he made his first @tinytapeout asic design.
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logic destroyer
@splinedrive1 Jun 2024
I motivated my 9-year-old son to develop an 8-bit binary counter as an ASIC using Wokwi, following certain instructions. Here is the result. @WokwiMakes @tinytapeout @UriShaked @matthewvenn #wokwi #asic #dff #binary #counter #revolution #logicDestroyer generation change, game changer The future belongs to our KID chip designers.
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logic destroyer
@splinedriveOct 23
My son Kian was only nine years old when he made his first @tinytapeout asic design.
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Matthew Venn@matthewvenn25 Nov 2024
Introducing the Zero to ASIC analog course! youtu.be/wM4cobfjMMQ Don't miss the Black Friday discounts - join the newsletter for $150 off on Friday: zerotoasiccourse.com/newslet… Full course details: zerotoasiccourse.com/analog/

Introducing the Zero to ASIC analog course!

Course details: https://zerotoasiccourse.com/analog/Newsletter: ht...

youtube.com
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Matthew Venn@matthewvennOct 23
I designed an analog mixed-signal radio chip with an AI agent: about 700 prompts in a week, and it's now submitted for tapeout. Here's how it went at each step of the design, the times it was confidently wrong, and how I caught them. youtube.com/watch?v=c53n4mH_… #ASIC #opensource

I put AI to the test on analog chip design.

I spent a week designing a radio chip with an AI agent. In this vid...

youtube.com
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Machdyne UG@machdyneOct 23
Zeitlos #FPGA SOC/OS now has up to 256 colors in game mode. 🌈
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Marcelo Samsoniuk
@samsoniukOct 22
wow! welcome to the SLOP-V! 🤣
bubble boi
@bubbleboiOct 22
I just had AI write an entire RISC-V core, put it on an FPGA, compile C code into a custom ELF format, boot the core, and run the program. I read ZERO of the code. Someone come up with a good name for the core.
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Vacation begins!
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logic destroyer
@splinedriveOct 19
StealthV – Custom RISC-V Quad-Core Linux SoC | Marketing Video
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StealthV – Custom RISC-V Quad-Core Linux SoC | Marketing Video
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Marcelo Samsoniuk
@samsoniukOct 19
well, I always talk about this but as a joke! 🤣
kache
@yacineMTBOct 19
why don't we make computers store memory as photons in the optical fiber that they use to transfer information between eachother, rather than in volatile or non volatile memory?
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Tiny Tapeout
@tinytapeoutOct 19
These one-of-a-kind Tiny Tapeout x wafer.space breakout boards have 52 unique open-source designs on them! Check out the behind the scenes of how they were made: crowdsupply.com/wafer-space/…
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