Anant Nivarti

Most people look at @OpenAI's Jalapeno and think they built a magic black box that replaces GPUs overnight, but this couldn’t be further from the truth. OpenAI's Jalapeno contains a rich set of system architecture tradeoffs and design methodology improvements that went into the chip design that all semiconductor engineers and technical leaders can learn from. Throughout this design, OpenAI leveraged an open source tool Google XLS that aided in block level optimization for PPA and formal verification leveraging their frontier models. Google XLS had its benefits in contributing to a shorter timeline, but I think the iterative, cross-domain (and often messier) nature of work is perhaps the more significant factor. This post is an advanced case study into Jalapeno based on their presentation deck from @hotchipsorg and related material. I will cover the entire architecture, including what motivated it, what tradeoffs and alternatives were likely considered by their leadership, and how AI added value. After writing this post, it makes me wonder whether AI should be best tailored to enhance the steps within the current “waterfall” chip design methodology or enable a more iterative methodology with a new skillset. siliconcodesign.com/p/an-adv…

I feel like the reason "AI for chip design" has vast opinions is that the actual benefit all depends on the complexity of the chip and how much sunk time and $ is on the line. AI can definitely automate simpler, "toy" chips with open source tools quickly, but not complex, market-leading chips with $50M cost. People often misconflate the benefits that AI has on the former case easily translate to the latter.