30-yr Optics & Semiconductor Engineer. turned 8x Founder. Now Canadian buy-side investor hunting physical bottlenecks in AI infrastructure. Silicon,
Toronto Canada
Joined December 2022
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The Indium Phosphide Bottleneck: Why Silicon Photonics Rescued Pluggable Optics—and Triggered a Global Laser Wafer Crisis
Inside the 7-stage photonic supply chain, China's MOFCOM controls & the 2.1x CW wafer yield salvation inside 1.6T transceivers.
Culper Research (@CulperResearch) published a forensic 17-part short thesis on Nvidia ($NVDA) detailing a Southeast Asian GPU diversion pipeline involving Alibaba, Megaspeed, and Aivres.
While the corporate registry forensics are detailed, the short thesis commits a fatal semiconductor economics error:
The "$30B Revenue Air Gap" Fallacy: Culper assumes that freezing Southeast Asian smuggling wipes out $30B in Nvidia revenue. This treats Nvidia as demand-constrained. In reality, Nvidia is strictly CoWoS-allocation-constrained. TSMC packaging lines are 100% committed through late 2026.
The Margin Expansion Paradox: Diverted H200 chips carry regulatory discounts and distributor friction. If Washington closes the Singapore/Malaysia loophole, Nvidia simply reallocates those scarce CoWoS packaging slots to backlogged US hyperscalers waiting 12 months for GB200 and GB300 NVL72 racks. Reallocation increases blended ASP and expands gross margins.
Culper mapped a smuggling corridor, but mispriced the physics of wafer fungibility.
$NVDA $BABA $SMCI
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Menlo Ventures 2026 Enterprise AI data provides empirical proof of the structural crossover buy-side models have tracked:
For every $1 spent building frontier models ($102.5B), enterprises now spend $1.70 deploying them ($176.8B). Three takeaways for tech capital allocation:
1. The Death of the "No Software ROI" Thesis: Deployment spend exploded 5.4x YoY to $176.8B, officially outstripping model development. Downstream enterprise software monetization is scaling faster than upstream model CapEx.
2. Coding Agents as the ROI Engine:
Spending on coding agents grew 7.7x YoY to $34B, surpassing generic chat assistants ($25B). Enterprises pay aggressively for direct engineering labor augmentation ($150k-$300k developer salaries), driving the 7.5x explosion in inference infrastructure ($94.2B).
3. The Silicon Rotation:
The 1:1.7 deployment crossover marks the permanent hardware shift. Training relies on raw FP8 matrix FLOPs, but enterprise agentic deployment is memory-bandwidth-bound. Hardware value concentrates into HBM4 bandwidth, 72-GPU NVLink scale-up domains, and server host DRAM.
$MSFT $AMZN $GOOGL $NVDA
Menlo Ventures: Enterprise AI
"For every $1 the industry spends building AI models, enterprises spend about $1.70 putting them to work."
"We estimate that Anthropic and OpenAI alone account for 25%+ of AWS, Azure, and Google Cloud revenue, with much of that spend going to training. That investment only pays off if enterprises keep putting models to work, which agents are now driving."
$AMZN $GOOGL $MSFT $NVDA $AMD $META
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1/5 Damnang (@damnang2) raised a vital thesis: NVIDIA despecing Rubin Ultra from 288GB (16-Hi) to 192GB (8-Hi), alongside 2028 mega-fabs (Yongin Y1, Micron Idaho, P5), signals a memory downcycle. Buy-side models must stress-test this against 100 days of new supply-chain data.
4/5 Variable 3: Contractual Lock-in. Suppliers shifted 60-70% of DRAM capacity into 3-5 year Long Term Supply Agreements (LTAs). With 2027 HBM contract negotiations securing +70% to +140% pricing step-ups, memory gross margins have decoupled from open spot-market volatility.
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The Hana Securities and TrendForce server DRAM forecast reveals the structural anomaly defining the 2026-2027 semiconductor supercycle:
In historical memory cycles (2018, 2021, 2023), bit output expansions inevitably drove the oversupply rate to +10% to +15%, collapsing ASPs. In this cycle, despite server DRAM bits almost doubling from 14,000M to 27,000M (mil 2Gb) through 1Q27F, the oversupply line remains pinned strictly below 0%.
Three physical mechanics keep the market in continuous structural deficit:
1. The HBM Wafer Tax: Fabricating HBM consumes 3x to 4x the wafer area of standard DDR5. Wafers allocated to Blackwell and Rubin clusters permanently cannibalize commodity server DRAM starts.
2. Agentic Host Sizing: Agent runtimes (multi-step tool orchestration, Wasm micro-VMs, and 1M+ token KV cache offload) pushed server memory density from 4-8GB/core to 16-32GB/core, generating an unprecedented 96 EB demand wave.
3. Lithography Caps: Transitioning to 1c and 1d nodes mandates 7+ EUV layers. ASML tool output capped at ~55 Low-NA scanners annually prevents cleanrooms from flooding wafer starts.
Pricing power and gross margins for Micron ($MU) and SK Hynix ($SKHY) remain structurally protected through 2027.
$MU $SKHY $ASML
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The infographic ranking Samsung, SK Hynix, and Micron ($MU) in the global top 7 for semiconductor patents exposes the dual barrier protecting memory gross margins:
The Legal Embargo Wall: The Big 3 hold reciprocal cross-licensing pacts spanning decades of foundational cell layouts, charge-pump circuits, and TSV micro-bump structures. Any sovereign challenger attempting to export advanced DDR5 or HBM to western markets faces immediate US ITC Section 337 patent exclusions.
Unpatented Process Telemetry: The true manufacturing barrier never appears in patent filings. It sits in proprietary fab telemetry:
- Cryogenic dry etching of capacitor trenches exceeding 50:1 aspect ratios.
- Atomic layer deposition of high-k dielectric films to prevent sub-10nm quantum leakage.
- Proprietary epoxy chemistry in liquid molded underfill (MR-MUF) to control thermal warpage across 16-high HBM4 stacks.
The Sovereign Capital Limit: Subsidies can purchase cleanroom tools from ASML, Lam, and TEL, but cannot buy 25 years of yield learning curves.
Buy-side takeaway: Structural memory deficits cannot be solved by new entrants dumping volume. Advanced DRAM pricing power remains consolidated within the oligopoly.
$MU $SKHY $ASML
A critical reminder from semiconductor physicist Dr. Maksym Plakhotnyuk on advanced packaging bottlenecks: cleanroom capacity reflects atomic process control rather than floor space.
Sell-side models assume building cleanrooms linearly doubles CoWoS and HBM output. Physical reality on the fab floor operates under three harsh yield constraints:
Sub-Nanometer Thin Film Uniformity: In 16-high HBM4 and CoWoS-L, inter-die dielectric layers thin down to single microns. Nanometer-level ALD thickness variances cause catastrophic dielectric breakdown under thermal cycling.
CMP Planarization Limits: Direct copper-to-copper hybrid bonding mandates surface roughness below 0.5nm. CMP dishing of a single nanometer creates interface micro-voids and open circuits that destroy compound packaging yield.
Thermal Warpage and CTE Mismatch: A 6x coefficient of thermal expansion mismatch between silicon interposers (2.6 ppm/°C) and organic ABF substrates (16 ppm/°C) causes severe die warpage during thermal compression bonding.
Advanced packaging capacity cannot be bought with CapEx alone. Yield is governed by process physics, maintaining structural supply tightness across 2027.
$TSM $NVDA $ASML
Agree on packaging. CoWoS and HBM set the ceiling. Inside them, yield sits in bonding and very thin films. Capacity is not only floor space. It is process control. #AdvancedPackaging #HBM
SemiAnalysis decoding of CXMT 4F² DRAM roadmap reveals the micro-physics behind Chinese semiconductor substitution:
The Two-Wafer Penalty: CXMT 14nm 4F² cell is actually ~10% larger than its G5 cell. The ~10% net die density gain comes entirely from moving peripheral logic to a separate wafer via hybrid bonding. Unlike 3D NAND (YMTC Xtacking) where two-wafer costs amortize across 200+ vertical layers, planar DRAM burns two full 300mm wafer starts for a single memory plane.
Compound Yield Decay: Total manufacturing yield equals cell yield multiplied by peripheral yield multiplied by bonding yield (Y_total = Y_cell × Y_peri × Y_bond). At volume, composite yield drag destroys commercial cost-per-bit economics.
Geopolitics Over ROI: Barred from ASML EUV scanners, CXMT is substituting state capital and cleanroom wafer starts for lithography resolution. This secures captive domestic server supply, but cannot compete on global open markets.
Buy-side takeaway: CXMT cannot trigger a global DDR5 supply glut. Micron ($MU) and SK Hynix retain pricing power, protected by ASML scanner caps and HBM4 cleanroom cannibalization.
$MU $ASML
CXMT is talking up its 4F² DRAM roadmap again. At its October 30 earnings briefing, the company mentioned its first 4F² DDR5 RDIMMs are targeted for sampling by year-end. (1/6)🧵
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The simultaneous rally across $BE, $ALAB, $VICR, and $COHR illustrates a core buy-side rule: when physical laws govern computing, hardware bottlenecks capture the economic rent.
While retail debates GPU market share (Nvidia vs AMD vs custom ASICs), this basket monetizes the inescapable physical constraints of every AI cluster:
Time-to-Power: Utility substation queues in PJM and ERCOT stretch past 36 months. Bloom Energy ($BE) solid oxide fuel cells provide on-site, behind-the-meter baseload to energize data centers immediately.
Signal Integrity: At PCIe 6.0 and 224G SerDes, high-frequency signal attenuation limits copper trace reach to under 5 inches. Astera Labs ($ALAB) retimers are mandatory across every compute and switch tray.
Core Power Delivery: Feeding 1,000A+ at sub-0.8V to Blackwell and Rubin dies causes severe I²R resistive losses. Vicor ($VICR) vertical 48V-to-core power delivery modules prevent motherboard thermal runaway.
Optical Scale-Out: Disaggregated gigawatt clusters require massive 800G and 1.6T transceivers. Coherent ($COHR) supplies the underlying EML lasers and optical engines.
Dollar content per rack across these four domains compounds at 40%+ through 2028. Earnings beats faded on macro noise create prime accumulation windows.
$BE $ALAB $VICR $COHR $NVDA
Nothing better than watching the stocks that printed RECORD numbers into faded reports finally pump hard.
$BE, $ALAB, $VICR, $COHR just to name a few. The market ignored the earnings for a week, it never ignores them forever.
This is exactly the setup that I love.
Record results faded on sentiment are not a warning, they are an entry.
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While retail treats the Taiwan semi surge (+4.94% TAIEX) and optics rally ($COHR +10%, $LITE, $NBIS) as a meme on the Jensen Huang scandal, buy-side desks are pricing three cold mechanics:
Geopolitical Panic Pull-Forward: The scandal signals imminent closure of H200 export channels. Chinese hyperscalers and sovereign funds are aggressively front-running trade restrictions, pulling forward orders for non-US ASIC design (MediaTek +9.9%) and niche DRAM (Winbond, ESMT).
Network Disaggregation & Optical Tailwinds: Regulatory tightening on US racks accelerates the spillover of AI clusters to Europe and Asia. Disaggregated scale-out clusters cannot rely on monolithic NVLink copper racks; they require massive deployments of 800G and 1.6T optical transceivers ($COHR, $LITE). European-neutral clouds ($NBIS) capture fleeing sovereign workloads.
The Physical Ledger Overrules Drama: Personal headlines alter zero TSMC wafer starts, CoWoS allocations, or hyperscaler balance sheet CapEx. When Monday opened with zero canceled purchase orders, macro shorts were forced into immediate covering.
$NVDA $COHR $LITE $NBIS
I did not expect everything in the AI trade from $LITE to $NBIS to rally today
Off the “honeypot catalyst”?
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The market narrative that peak AI CapEx equals peak earnings for AMD ($AMD) fundamentally misprices the agentic computing transition and server CPU operating leverage:
The Agentic CPU Architecture: Static LLMs run on GPUs, but agentic runtimes run on CPUs. Multi-step tool execution, Python sandboxing, Wasm micro-VMs, and database state tracking require 16-32GB DDR5 DRAM per core and low-latency branching. Venice with 16-channel DDR5 and high core density is tailored for agent runtime orchestration.
The Host Node Monopoly for Custom ASICs: NVIDIA bundles Grace ARM CPUs into proprietary NVL racks. Non-NVIDIA accelerators (OpenAI custom silicon, Google TPU, AWS Trainium) require x86 host nodes to preserve existing virtualization and Linux software stacks. AMD EPYC has locked in over 80% share of this rapidly scaling ASIC host market.
Financial Operating Leverage: Datacenter CPU gross margins sit at 65%+. Doubling server CPU revenue through 2027 while holding OpEx growth below 15% yields dramatic operating income expansion. AMD earnings are decoupling from merchant GPU sentiment.
$AMD $INTC $NVDA
THE LATEST EPISODE OF THE DEEP END JUST DROPPED
The new AI economy is agentic and agents need GPUs to think and CPUs to act which is why I think $AMD is uniquely positioned with Venice launching across 240+ platforms, Helion packing 144 CPUs into a single rack and OpenAI choosing EPYC to host its custom accelerators.
I just think market is mistaking peak CapEx growth for peak earnings when AMD expects server CPU revenue to double in 2027 while expenses grow at less than half rate of revenue.
CoreWeave ($CRWV) signing a multi-year Blackwell compute deal with autonomous driving lab Wayve highlights three structural trends buy-side models must price:
Embodied AI as a Dense Compute Sink: Video-native foundation world models consume vastly more compute than text LLMs. Ingesting multi-camera high-fps streams and generating future physical states requires sustained Blackwell FP4 throughput and non-blocking InfiniBand scale-out fabrics. Autonomous driving is becoming the largest non-frontier-lab training workload.
Neocloud Quality Bifurcation: While generic GPU rental clouds face collapsing MOU conversions (30-40%) and leasing price wars, CoreWeave insulates its cash flows with multi-year take-or-pay contracts from well-funded labs (Wayve backed by SoftBank, Nvidia, and Microsoft).
The Nvidia Flywheel: Nvidia ($NVDA) holds strategic equity in both CoreWeave and Wayve. This capital recycling loop directs venture funding into dedicated cloud contracts that directly monetize through Blackwell and Rubin hardware sales.
$NVDA $CRWV
Headlines framing Google new TPU systems as an Nvidia killer misunderstand hyperscaler workload segmentation and semiconductor physics:
Internal Margin Defense vs Merchant Silicon: Google builds TPUs to protect Search and Gemini token inference unit economics. Outside of internal workloads, third-party GCP enterprise customers continue buying GB200 and GB300 NVL72 racks. TPUs defend Alphabet margins; they do not displace Nvidia merchant demand.
Packaging Reality: TPUs do not escape the physical bottleneck. Every TPU pod consumes TSMC CoWoS packaging capacity and HBM wafer starts. Google scaling TPUs simply shifts TSMC allocation from third parties to internal ASIC lines. The balance-sheet winner from TPU volume is design partner Broadcom .
$NVDA $GOOGL $AVGO $TSM
The headline focuses on Morgan Stanley maintaining $1.6T in hyperscaler capex through 2027, but the critical alpha sits on page 12: a 5GW US data center push-out from 2028 to 2029.
Post-midterm regulatory reviews in Texas and Ohio are forcing a 4% YoY drop in 2028 grid additions before a 38% rebound in 2029. Three structural takeaways for buy-side models:
The 2028 Air-Pocket: Capex dollars stay flat on accounting ledgers, but physical rack installations will stall. Hardware ODMs and component vendors face an inventory digestion window across 2028 until substation interconnections catch up.
Geographic Dispersion: Hyperscalers are redirecting 20GW of builds overseas (Europe, Asia) and to deregulation-friendly states like Louisiana. Power availability dictates geographic capex, not local tax incentives.
Structural Advantage for Balance Sheets: Slower grid energization props up compute lease rates. Hyperscalers with 30%+ ROIC and internal workloads benefit, while leveraged Neoclouds cannot service debt across a 12-month grid delay.
$MSFT $AMZN $GOOGL $NVDA
People often ask how to maintain daily institutional-grade semiconductor research without burnout. The mechanics come down to three operational rules:
Primary data over narrative commentary.
Ignore financial headlines and track the physical constraint layer directly: wafer allocations, packaging lead times, utility power queues, and SEC purchase commitments.
Maintain an ongoing ledger.
Never write an analysis from scratch. Keep an active quantitative model of the supply chain. When an expert call or earnings report drops, it is simply a parameter update to existing equations.
Respect physical laws.
Hype cycles fluctuate with sentiment, but silicon yields, interconnect widths, and thermodynamics do not lie. When your framework is anchored in hardware reality, the signal stays consistent.
$NVDA $TSM $ASML
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The leaked OEM channel check confirms three structural shifts buy-side models must price for 2027:
1. The 6,000 Rubin rack number reflects a single OEM, yet represents massive physical strain. At 72 GPUs and 130kW per rack, 6k racks equals ~430k GPUs and ~780MW of load. With 1-3 month utility grid delays and sub-60% HBM4 yields, physics caps shipments, not customer appetite.
2. Neocloud financing has broken. Q3 MOU-to-binding-PO conversion collapsed to 30-40% as GPU rental price wars crush unit economics. 90% of GB300 NVL72 shipments flow directly to balance-sheet hyperscalers, while speculative clouds face balance sheet liquidation.
3. The memory margin inflection is here. Spot DRAM up 4x pushed PC memory BOM to 38%, equalizing standard DRAM margins with HBM. Samsung shifting wafer capacity back to commodity DRAM in Q4-2026 proves DDR5 supply limits are actively cannibalizing AI memory starts.
$NVDA $MU $DELL
Expert Takeaways: Rubin, Neocloud, Power and MOU
> GB300 Production & Delivery: A global AI-server OEM achieved ~700-rack GB300 NVL72 capacity in Q3-2026, delivering ~600 racks on schedule, with 90% going to CSPs.
> Vera Rubin Delayed to Q1-2027: Next-gen Vera Rubin output (<100 racks originally set for Dec-2026) shifted to Q1-2027 due to power-grid bottlenecks and low HBM4 yields; 2027 target is 5,000–6,000 racks at ~$8M ASP.
> Widespread Power Delays: Data center grid connection backlogs cause 1–3 month deployment delays across all customer tiers depending on utility queues.
> High Risk in Neocloud Pipeline: Q3 MOUs from compute-rental clients grew <50% QoQ, with only 30–40% converting to binding POs due to tight financing and weak unit economics.
> Price-War Risks & Hyperscaler Stability: Commodity compute leasing drives price wars and tentative H1-2027 follow-on POs for Neoclouds, while self-funded hyperscalers maintain high conversion rates.
> 2027 OEM Quota Shifts: Dell’s GB300/Vera Rubin allocation will be flat-to-modestly higher, while Lenovo’s NVL quota rises from 7% to 10% following system audits and NVIDIA qualification.
> Severe Consumer Hardware Slump: 2026 PC shipments are forecasted at 63M units (50% AI PCs); Q3-2026 PC shipments fell 22–23% YoY, while handsets dropped 40–50% YoY due to memory cost inflation.
> Memory Cost Surge & ASP Strategy: DRAM spot prices quadrupled vs. Q2-2025, pushing memory BOM share from 18–20% up to 35–38%; vendors rely on higher ASPs and premium mix to offset soft entry-level demand.
> Samsung Wafer Shift & 2027 Recovery: Samsung is expected to shift capacity from HBM back to DRAM in Q4-2026 as DRAM margins match HBM, helping plateau memory prices in Q1-2027 and spark a PC shipment recovery by Q3-2027.
> Aggressive OEM Inventory De-Risking: Tier-1 PC OEMs cut DRAM coverage from 6 to 3–4 months and CPU coverage to 2 months, holding finished goods at 30–40 days to avoid high-cost inventory exposure.
Reminder: not all expert provided information may be accurate. Please be advised.
$NVDA $MU $SKHY $NBIS $CRWV $DELL
1/5 The expert call confirms Intel ( $INTC )EMIB-T assembly yield sits at 40.5%. While eliminating full-wafer silicon interposers cuts theoretical BOM cost by ~40% vs CoWoS-L, scrapping 60% of completed packages destroys host wafer economics. A 6x CTE mismatch between silicon bridges (2.6 ppm/°C) and organic ABF (16 ppm/°C) causes warpage during bonding. CoWoS-L retains 80%+ share through 2028.
Believing Intel ($INTC) EMIB will win on a "40% BOM cut" overlooks the asymmetric cost of packaging scrap.
The Scrap Trap: A 40% substrate BOM discount saves ~$600. Yet multi-die AI packages carry $30,000 to $50,000 in prime 3nm host dies and HBM. At a 40.5% assembly yield, scrapped packages destroy tens of thousands of dollars in good silicon per functional unit.
Thermodynamics over Operations: A 6x CTE mismatch (2.6 vs 16 ppm/K) between silicon bridges and raw ABF is fundamental physics. At 260°C reflow across large substrates (>100x100mm), warpage shears 45um microbumps.
Customer Risk: Hyperscalers will refuse to commit billion-dollar tapeouts to a packaging line with a 60% scrap rate.
Until assembly yield crosses 85%, BOM savings remain completely submerged by host wafer write-downs.
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