FPGA Bandera (@LilElseCaller) header
FPGA Bandera (@LilElseCaller) profile picture

Building the perps dex. · Ex DeFi Engineer at @SushiSwap · Hackathon Winner @Base

40.7606°N, -73.9835°W
Joined October 2014
Photo by FPGA Bandera (@LilElseCaller)Photo by FPGA Bandera (@LilElseCaller)Photo by FPGA Bandera (@LilElseCaller)Photo by FPGA Bandera (@LilElseCaller)Photo by FPGA Bandera (@LilElseCaller)Photo by FPGA Bandera (@LilElseCaller)Photo by FPGA Bandera (@LilElseCaller)Photo by FPGA Bandera (@LilElseCaller)Photo by FPGA Bandera (@LilElseCaller)Photo by FPGA Bandera (@LilElseCaller)
Reindustrialize.
the reindustrialize poasting will continue until the hoes are paralyzed with fear
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If you're Catholic and going to Breakpoint in London, hmu so we can go to vigil Mass together on the 14th!
Through work, one develops as a person, provides for family needs, expresses one’s own talent, participates in social life, and builds a better world by collaborating in God’s creative work. The real challenge is to offer everyone opportunities to make the most of their abilities. Unemployment, exploitation, and working conditions that endanger health and life itself are unacceptable (Gaudium et Spes, 67). #GeneralAudience
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We achieved natural markets in DeFI Silicon so market makers can freely test sending orders directly into an FPGA!
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I get asked a lot about how to get started with FPGAs. This blog and @ATaylorFPGA’s content are two great resources for anyone looking to dive in.
One .t27 spec, five targets: 1 ms native object, 5 ms JIT test verdict, arm64 asm listing, CI reference verdict, Verilog RTL. t27b compiles ~70-100x faster than clang, artifact 28x smaller. Measured, commands included: t27.ai/blog/one-spec-five-ta…
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I feel like optimizing k-way partitioning after my testnet is live.
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This is really interesting for edgeAI & smaller speciailzed models:)
We asked GPT-6 Astra to edit Qwen3.5-0.8B weights to improve math. It directly changed only 0.016% of weights, fixing 0.8B's reasoning loops & improving math up to 6x and even instruction following 3x, without gradients or training. We call this Weight-Space Programming: frontier LLMs can now natively read/write neural network weights! 🧵 Blog: rikiyat.github.io/blog/weigh…
Readers added context they thought people might want to know
LLM was given weights explicitly as text in prompt and used code/forward passes (per authors' logs) to ablate Qwen looping direction, a known thinking-mode issue per model card. Primarily fixed repetition in that mode, not general 'natively' improving weights/math. rikiyat.github.io/blog/weight-sp… github.com/RikiyaT/lm_und… huggingface.co/Qwen/Qwen3.5-0… huggingface.co/RikiyaT/Qwen3.…
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May STEM include artists again?
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time to migrate that 3.3% of my repo to systemverilog.
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I couldn't find a good-quality version of one of my favorite art pieces, so I upscaled it using AI.
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I'm so lucky to go to work everyday
I am so lucky to go to work everyday! Atech.dev
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what are my FPGA chuds cooking today
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Know the difference
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And the band begins to playan
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This is what I'm talking about when I say that a couple, talented FPGA companies or even engineerings, can push frontier at MUCH cheaper price, at least on RTL design. It's impressive that no one cares enough, as these models should be the ones that unlock real speed for non RTL frontier.
First local LLM building a MicroBlaze System for the SCU35 using a local LLM no frontier model using AMD Ross.
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yesterday I went to sleep without any RTL routing and I felt like I was wasting my day.
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blockchain architect. blockchain as solana, not as anchor blockchain as ethereum, not as solidity.
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After 3 or 4 iterations, Atech will produce wearables that consumers will buy. And they probably don't even know it yet
It has never been easier and faster to get into hardware. Modular hardware you can vibe-code. Atech.dev
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I hope everyone realizes the huge opportunity we have to change the world now that 95% of software is solved.
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i need to improve my memetic arsenal
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