リソグラフィエンジニアの戯言 retweeted
院生の時代
彼のPROLITHに
触発されて
初期的な光学系の
MTFからウェハ上
の結像一連工程を
プログラムした
記憶がある
このような人だとは
知らなんだ
リソグラフィエンジニアの戯言 retweeted
Just watched a Zeiss talk from 2020 on a lens modification they made for ASML’s immersion scanners. It’s a useful real-world example for the current speculation about how long it takes to develop a fab tool like this. Posts on this subject tend to draw a certain kind of response from people outside chip patterning. Instead of generalized hypotheticals, consider an actual case.
The name of the game for a scanner is commercial overlay and throughput. If a tool does not meet both specs, it has no home in a fab. That is as simple as it sounds, and it has nothing to do with geopolitics. Overlay is how accurately the scanner can print one chip pattern on top of another. Throughput is how many wafers per hour it can process. These specs compete: the faster the system runs, the less accurately it can place a pattern.
Modern lithography tools have to place patterns at the single-digit nanometer scale while processing, in the immersion case, about 300 wafers per hour, roughly a wafer every 10 seconds. Each new immersion tool shaves a fraction of a nanometer off the overlay budget. Zeiss’s work here is just one of many upgrades that go into a new litho tool.
Zeiss only knew what to do because it had absorbed years of fab data and the exposure of millions of full-stack product wafers. Immersion tools are not developed in a lab vacuum. They are developed on the production floor. In this talk, Zeiss cites a set of DRAM layers that needed the upgrade so the device could keep scaling and adding bits. That is point one: you need real chip data on specific devices and layers, where there is an actual problem to fix.
Point two is prior art. Zeiss was building a new manipulator inside the lens to make overlay corrections on top of corrections already in place. The slide shows this as the third generation of lens manipulator. Flat lenses are not enough. Active correction is required, especially to compensate for lens distortion caused by heating. Speed matters here, and these lenses heat up in operation. The DRAM-layer example matters because different chip patterns heat the lens differently.
Point three is the timeline. In 2020, after years of fab data, Zeiss had a new lens prototype that could be dropped into the immersion tool ASML was then selling, the NXT:2000i. They could demo the upgrade and show that it worked. It still took another four years before that upgrade shipped in a production tool, the NXT:2100i.
A DRAM customer of ours later told me how important the 2100 was for enabling the next node. Zeiss’s work was only one of many tool modifications in that next-generation immersion system, and it was years in the making. It rested on thousands of earlier lens tweaks and millions of wafers run to isolate the overlay problem.
I hope this example from immersion lithography helps explain my view of scanner development timelines. These are among the most complex production machines ever built. They require global overlay matching across an entire fab at extraordinary tolerances. It is very difficult, if not impossible, to apply these lessons in parallel just to go faster.
🤖 Made with AI
リソグラフィエンジニアの戯言 retweeted
Understanding what’s happening at Nikon right now can help put this whole semi sell-off into perspective.
They make the NSR-S636E immersion scanner, which was every bit as good as ASML’s top machine when it was released a few years ago. However, it was also an absolute commercial dumpster fire. They're shipping zero this year during the AI boom. Talk about an outlier.
They finally had to throw in the towel last February and admit their immersion scanner design was a dead end. Their new strategy is to enable their systems to match ASML’s tools on the MMO spec.
The timeline? Five years. First production tools in 2030.
So here we have Nikon—who can already build a 7nm-capable immersion system and has been shipping immersion tools for 20 years—throwing their entire tool design in the garbage in 2026 and starting over. Dive down that rabbit hole.
リソグラフィエンジニアの戯言 retweeted
ちょwww
プシューw
youtu.be/flWbdsjVnn4?si=rBb0…
リソグラフィエンジニアの戯言 retweeted
BUMP OF CHICKENファンのワイ
2014年にrayという曲で初音ミクとコラボをしましたが、コラボなしの曲をApple Musicのカラオケ機能で聴いてみると、こちらにもミクさんの声が隠れていることに気付いて感涙
リソグラフィエンジニアの戯言 retweeted
部材の入手は近年ますます容易になっています。発送商品表記を「PC部品(ポリウレタンカバー)」とするサービスもあり秘匿性も保たれます。最薄で0.01mm、耐久性も日進月歩です。日本メーカのシェアは根強く、あらゆるサイズに対応した製品もあります。
..最後のポストだけネタです。嘘ではない。おわり
リソグラフィエンジニアの戯言 retweeted
ASML開発者の、ペリクル開発でアハ体験
「日本のカタナソードを作るドキュメンタリーを見てたんだ。何層にも重ねた鋼鉄で作るんだけど、翌日それを同僚に話したら『いいね!』ってなって、2週間後には1stサンプルができたんだ」
って話、嫌いじゃないポヨ。
asml.com/en/news/stories/202…
リソグラフィエンジニアの戯言 retweeted
ペリクル内製について(光源問わずのお話)
「ペリクル内製」には2つのニュアンスがあります。ペリクルそのものを作るか、ペリクルの張り替えを自前でやるか。主に後者のお話。
ペリクル張り工程はマスク製造工程の最終ゲートであるパターン検査の直前ということもあり、非常に繊細な工程です。→
リソグラフィエンジニアの戯言 retweeted
「ぺ」
撃ち尽くし
そっとペリクル
はずす君
#ブラック半導体かるた
リソグラフィエンジニアの戯言 retweeted
ご参考まで
もちろん透過率が上がれば熱上昇は緩和されますし、この記事は2016年のものなので状況は変わってると思われます。(この時期はペリクルそのものの是非もはっきりしてませんでしたし)
semiengineering.com/next-euv…
リソグラフィエンジニアの戯言 retweeted
めちゃ補足ですがペリクル仕様はSEMI P5で規定されています。改定ドキュメントをさらっと読みするだけでも勉強になるポヨン
downloads.semi.org/web/wstds…
メモ
カーボンナノチューブ(CNT)を用いたEUVペリクルをimecと共同開発したフィンランドのカナツ社、主力製品は同じくCNTを用いたADASカメラ用途のフィルムヒータや、車載用3Dタッチセンサ。
canatu.com/products/
リソグラフィエンジニアの戯言 retweeted
mass-production means the scanner's overlay and throughput spec.
"China could achieve a breakthrough with mass-production level domestic EUV technology within two years at the earliest, or within five years at the latest." -Richard Zhang, SMIC Founder, Jan 2026
リソグラフィエンジニアの戯言 retweeted
点呼で作業員の数が足りないらしい。
ふと見たらグレーチングの無い床がある。
何故かカラーコーン&バーの養生もしてない(憤怒)
#クリーンルームであった本当に怖い話ポヨ
リソグラフィエンジニアの戯言 retweeted
🧵 1/12: Elon Musk just replied "True" to the idea that he might start building lithography machines. Why? Because these insane $400 million beasts are the ultimate bottleneck for chips, AI, and the entire future of computing. Including speedrunning to a Kardashev Type 2 civilization.
リソグラフィエンジニアの戯言 retweeted
Grayscale lithography.
People crave high-tech EUV stuff, but old-school i-line litho is Space Cowboy. The MEMS world relies on grayscale lithography to print 3D patterns at the nanoscale. This is used to make microlenses, microfluidic print heads, and just about every type of sensor you can think of.
The semi industry never made the ideal grayscale photoresist for the MEMS market. Instead they take typical DNQ i-line resists and, by process means, try to make them work like a decent grayscale photoresist. But this leaves so much on the table in terms of patterning performance.
I dream of the ideal grayscale photoresist. Untapped market. It actually does the opposite of what a conventional photoresist does. Literally 100% opposite for contrast and etch resistance. It deserves its own special photoresist chemistry.





























