systems engineer, ml compilers, FPGAs, EDA, GPUs and fun
Joined January 2023
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Pinned Tweet
our talk 'No-ISA is the best ISA' is now live - check out the video where we break down our FPGA ideas at @Vicharak_In
Shreeyash Pandey retweeted
Everyone's trying to make CPUs faster.
I’m trying to make them worse.
New project: CPU deoptimization.
Searching for the slowest possible machine instructions
x86 single instruction record:
198,002,498,236 cycles, 62 seconds
The assembly hall of shame: github.com/xoreaxeaxeax/asm-…
Shreeyash Pandey retweeted
Baby has gotten good at identifying “dada” but still struggling with surrealism, cubism, even baroque.
New blog post on register renaming in CPUs
fp32.org/register_renaming.h…
Vince Gilligan really loves pour over judging by the screen time that black coffee gets in BCS. It's the beverage of choice - Jimmy, Kim, Mike and even Hector can be found enjoying a nice cup of coffee every now and then.
Shreeyash Pandey retweeted
when a compiler engineer says something so vliwphobic you gotta hit ‘em with the itanium stare
Shreeyash Pandey retweeted
Currently reading the C++ templates I wrote yesterday and it's incomprehensible bullshit. We need better metaprogramming.
