So now we know that before Kirin9050, there only has one N+3 chip: Kirin 9030. (Kirin9030/ Kirin9030 Pro logic die is the same) It seems that SMIC is still struggling on N+3 process even under small die size. Kirin9030 chip is roughly ~5M shipping so far (Mate 80 Pro/ ProMax/ RS and Pura X Max). For Kirin9030 die size of 136mm2, one wafer can divide into ~400 chip. So even we assume N+3 yield is as poor as 50%… 5M chip only need 25K wafer in total… Even we estimate that there should be some stockpile, like extra 3M chip so 8M chip in total, still translate to 40K wafer only. It seems that Huawei preserve most of its N+3 volume to Mate 90 series. Mate90 basic/ Pro will use Kirin9030 chip, only ProMax and RS use Kirin9050. We can expect that Kirin9050 volume constrained will be more severe than Kirin9030 on Mate80 (Mate80 Pro use Kirin9030 but Kirin9050 is only for ProMax/RS). And if we give N+3 process 10K wpm (actually very low) and 1 year manufacturing time, there should be 120K wafer. So ~80K wafer available for Mate90. 10M Kirin9030 chip for Mate90 only need 50K wafer, and 30K wafer can divide into~3.75M Kirin9050 chip under 25% yield (considering the combination of package yield, and Kirin9050 die size is ~114mm2). Actually, I do not think Huawei now have 10M Kirin9030 chip/ 3.75M Kirin9050 chip for Mate80, so my calculations assumption condition should be lower- either the capacity (10k wpm) or the yield (50% for Kirin9030 and 25% for Kirin9050). No matter which one, it means SMIC still need to take a long road to increase the yield or output of the N+3 process even on small die. I do not expect that we can see the large ASIC/HPC die size chip on N+3 for soon. Ascend series chip will use logicfolding by 2030, perhaps we can also see the large AI chip with N+3 process by that time? Remember, steady and large amount of N+2 Ascend chip shipping is occurring on Ascend 950 with 0.5x mask size, three years after first SoC chip Kirin9000s was shipped. As for more challenging N+3, it may take longer time.

Shocking, Kirin 9030S is N+2, not N+3…. ————————— Mobile: Pura 90 Pro Max Die size: 122 mm2 Marker: Hi36D0G-GPCV100 CPP:63nm Cell height: 252nm SRAM cell area: 0.0315 —————————— Btw, Kirin 9050 Pro decap is on-going, and it is a chip using N+3 bond with N+2. Die size is even smaller than Kirin 9030S, hence far smaller than Kirin 9030.